1. Field of the Invention
The present invention relates to a timing control apparatus and a video processing system.
2. Description of the Related Art
Video display apparatuses have functions of receiving image signals to be displayed, performing video processing, and then outputting the image signals to a display device. Representative examples of such video display apparatuses include digital televisions and liquid crystal projectors. There are various types of video processing, such as a noise removal process, an edge emphasis process, and a super-resolution process for converting a low-resolution video to a higher-resolution video. Such video processing is a differentiating feature of video display apparatuses. The output of image signals comes in a wide variety of types, ranging from the output compliant with general VESA standards to signal formats and timings unique to each display device. Furthermore, a technique is commonly used whereby the cost of a video display apparatus is cut down by aggregating functions of receiving image signals, performing video processing and outputting the image signals into a single video processing LSI chip.
Digital televisions and personal computers typically have resolutions such as Full HD (1920×1080) and WUXGA (1920×1200). Meanwhile, with the development of higher-resolution display devices such as 4K2K (4096×2160) and ultra-high definition (7680×4320), dissemination of video display apparatuses including such display devices has begun. In the case of a high-resolution video, video input/output interfaces and memory interfaces with a larger bandwidth are required to receive image signals, perform video processing and output image signals, and moreover, the amount of operation increases. Therefore, there are times when a single video processing LSI chip cannot handle all processes.
In view of this, there is a method for spatially dividing a video and processing the video on a per-division basis in order to receive a high-resolution video, perform video processing and output the high-resolution video. One example is a method for horizontally dividing a video in half and causing two video processing LSI chips to operate in parallel in synchronization to receive image signals of the spatially divided video, perform video processing, and output the image signals to a display device. When causing two video processing LSI chips to operate in parallel, the image signals need to be output to the display device in synchronization. Therefore, in a two-chip configuration, two video processing LSI chips are caused to operate in synchronization by providing a module that generates a signal serving as a reference timing separately from the two video processing LSI chips and distributing the reference timing signal to the two video processing LSI chips. This configuration is shown in FIG. 6. A video processing apparatus 601 realizes functions of receiving image signals, performing video processing and outputting the image signals using video processing LSI chips. A video processing LSI chip 602 receives an L video which is a left-side video, performs video processing based on a reference timing signal 607 generated by a reference timing generation module 604, and outputs an L video+ to a display panel as an image signal. Similarly, a video processing LSI chip 603 receives an R video which is a right-side video, performs video processing based on the reference timing signal 607 generated by the reference timing generation module 604, and outputs an R video+ to the display panel as an image signal. The reference timing generation module 604 receives an input synchronizing signal 605 of the L video and an input synchronizing signal 606 of the R video, and generates the reference timing signal 607. Here, the reference timing signal 607 is generated by absorbing a difference between the two synchronizing signals, namely the input synchronizing signal 605 of the L video and the input synchronizing signal 606 of the R video, in consideration of conversion of a video frame rate and incorrect ordering of video frames between the input and the output.
According to Japanese Patent Laid-Open No. 10-84519, an additional module is not necessary because a video display apparatus that generates and outputs image signals shares a reference timing signal generation module built therein with another video display apparatus.
However, providing a module that generates a reference timing signal from a plurality of input image signals increases the cost of a video display apparatus. In the case where two divided image signals are separately input to video processing LSI chips, the two input image signals are not necessarily synchronous. A module that generates a reference timing signal needs to generate the reference timing signal with reference to synchronizing signals of the two image signals. In particular, in image signals compliant with SMPTE 425 (3G-SDI) and SMPTE 292M (HD-SDI), the synchronizing signals are embedded as timing codes in data. Therefore, a module that generates a reference timing signal increases the number of chip terminals for importing data signals and necessitates a decoding function of extracting the synchronizing signals, thus contributing to a further increase in the cost.
Moreover, the method described in Japanese Patent Laid-Open No. 10-84519 does not take into consideration a delay in the input image signals between video display apparatuses. Therefore, in a configuration using a plurality of video display apparatuses, it is difficult to exactly match the output timings of the image signals.